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THAUS1's avatar
THAUS1
Icon for New Contributor rankNew Contributor
3 years ago

MAX10 EPE M9K Fmax limit?

Hi,

I try to use EPE on MAX10. I generate accuTrack_early_pwr.csv file.

My design have some dual port block ram running at 320MHz:

BLOCK,M9K,count,1,ram_mode,"Simple Dual Port",ram_read_during_write,"new",ram_porta_fmax,"80",ram_porta_data_width,"36",ram_porta_addr_width,"2",ram_porta_depth,"4",ram_porta_ena_static_prob,"0.500000",ram_porta_write_ena_static_prob,"0.500000",ram_porta_read_ena_static_prob,"0.000000",avg_ram_porta_output_toggle_ratio,"0.000000",ram_portb_fmax,"320",ram_portb_data_width,"36",ram_portb_addr_width,"2",ram_portb_ena_static_prob,"1.000000",ram_portb_write_ena_static_prob,"0.000000",ram_portb_read_ena_static_prob,"0.500000",avg_ram_portb_output_toggle_ratio,"0.125000"

Import macro generate an error with a limitation at 260MHz :

1 errors encountered!
Line 37: Invalid clock freq on port B!
Cell value must be between 0.0 and 260.0
Skipping!

If in my design a change PLL frequency, import works fine. But I would like to use real frequency : 320MHz.

I don't understand where come from this 260MHz limitation. Is it related to this Table 31 of the datasheet?

If yes, there where no warning message about that into Quartus compiling flow.
Thanks for your help and advice.

14 Replies

  • SyafieqS's avatar
    SyafieqS
    Icon for Super Contributor rankSuper Contributor

    Noted. If that's so, since this case has been idling, I would put this to close pending and suggest you to create a new case mentining this case for follow up in future. In the meantime you may change the frequency as documented to avoid any further issue. Let me know any concern on this.


  • SyafieqS's avatar
    SyafieqS
    Icon for Super Contributor rankSuper Contributor

    Let me know if there is any update from previous reply