Max10 E144 I/O Assignment - Need clarify re. adjacent pins and cross-coupling

Cross talk will potentially be induced on any high impedance signal. So, yes - fast switching FPGA output edges may well couple onto a high impedance signal (including FPGA input signals) nearby, just as much as edges from other sources.

It is good practice to spread fast switching signals around the die and package although you're limited with that package. However, whether it's an issue can only be determined by you and your particular design. Do you see any functional behaviour you can't explain?

You mention you've seen a small amount of crosstalk. I assume you've observed this coupling by scoping the signal. This probing in itself adds extra loading onto a signal, increasing it's immunity to coupling - without the probe the signal is likely to be worse. How much? It's very difficult to judge. Extensive functional testing can build confidence but no more.

Coupling onto clocks will potentially be of greatest concern. Extra 'clock edges' - glitches - could propagate through the design causing widespread problems. This can be extended to any signal with an embedded clock that might feed a clock recovery circuit. Such signals are usually differential, thus guarding against the erroneous behaviour that might result from unwanted coupling. However, coupled noise on other signals could easily be of no consequence. It all depends how the signal is used.

So, whether it's appropriate to use the sets of I/O pads you describe or not can only be determined by you and your design. There's no universal right or wrong.

Cheers,

Alex