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Altera_Forum's avatar
Altera_Forum
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8 years ago

Max10 E144 I/O Assignment - Need clarify re. adjacent pins and cross-coupling

Hi,

Section 3.9 of the MAX 10 General Purpose I/O User Guide states the following, re. the E144 parts:

"There is strong inductive coupling on the MAX 10 E144 lead frame package. Glitch

may occur on an input pin when an aggressor pin with strong drive strength toggles

directly adjacent to it."

My question pertains to the following pin assignments we are currently using on the Max10 prototype board, as shown in the following screen capture of the Chip Planner:

(doesn't appear I am allowed to upload images yet - image I tried to upload did not appear; following will try to describe the issue).

What the Chip Planner view shows, is a brown/tan-ish rectangle with either two, or three I/O pads. My question is, in the case where there are three pads in one of these rectangular areas, is it ok to use the upper and lower of the three, and leave the center unconnected (or driven with ~constant signal)? Or, should only one I/O pad be used in each of these rectangular regions?

Note that we are driving all signals of concern at max drive strength since timing is tight. We see a small amount of cross talk with all three of the pins in one rectangle.

Would appreciate some experienced guidance here.

Thank you.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    I should have mentioned that the discussion in the Max10 UG referenced above, focuses on signals coming into the FPGA. I am assuming similar cross-talk can occur when the FPGA is driving output signals at max drive strength. If this is not the case, please clarify. Thanks again.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    Cross talk will potentially be induced on any high impedance signal. So, yes - fast switching FPGA output edges may well couple onto a high impedance signal (including FPGA input signals) nearby, just as much as edges from other sources.

    It is good practice to spread fast switching signals around the die and package although you're limited with that package. However, whether it's an issue can only be determined by you and your particular design. Do you see any functional behaviour you can't explain?

    You mention you've seen a small amount of crosstalk. I assume you've observed this coupling by scoping the signal. This probing in itself adds extra loading onto a signal, increasing it's immunity to coupling - without the probe the signal is likely to be worse. How much? It's very difficult to judge. Extensive functional testing can build confidence but no more.

    Coupling onto clocks will potentially be of greatest concern. Extra 'clock edges' - glitches - could propagate through the design causing widespread problems. This can be extended to any signal with an embedded clock that might feed a clock recovery circuit. Such signals are usually differential, thus guarding against the erroneous behaviour that might result from unwanted coupling. However, coupled noise on other signals could easily be of no consequence. It all depends how the signal is used.

    So, whether it's appropriate to use the sets of I/O pads you describe or not can only be determined by you and your design. There's no universal right or wrong.

    Cheers,

    Alex