Forum Discussion
Altera_Forum
Honored Contributor
8 years agoThis doesn't sound right to me. Everything you describe sounds appropriate. I don't think you're suffering from anything dual-purpose pin related. If JTAGEN is high then, regardless of the JTAG pin sharing setting, you should be able to access the device via JTAG.
Can you confirm that the JTAGEN pin is indeed high? Can you measure it? I appreciate you have a pull-up but I think something untoward is going on. --- Quote Start --- When I cycle power (re-loading the old, non dual use code), the JTAG recognizes the device again --- Quote End --- So you have something programmed into the CFM - right? Can you erase the FPGA's internal memory and work with a blank device? I'm concerned that the design in CFM is causing the problem, perhaps with the power rails. If a rail is dipping, due to excessive load, then the JTAG is likely to break. Cheers, Alex