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kw_arrow's avatar
kw_arrow
Icon for New Contributor rankNew Contributor
7 months ago

MAX10 DDR3 Timing

Hi, I need a definitive statement regarding the timing. The two attached screenshots were created with Quartus 23.1 but can also be found in 25.1. Although adjusting the temperature range reduced t...
Core Logic
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
6 months ago

Hi Korbinian,

 

Thanks for the update.

 

In this case, can you generate an example design from the DDR3 EMIF IP Editor(from current design) and compile the design?

If it an IP setting issue, we might be able see the similar timing in the example design.

 

Regards,

Adzim