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New Contributor
New ContributorMAX10 DDR3 Timing
Hi, I need a definitive statement regarding the timing. The two attached screenshots were created with Quartus 23.1 but can also be found in 25.1. Although adjusting the temperature range reduced t...
AdzimZM_Altera
Regular Contributor
Regular ContributorHi Korbinian,
Have you create a timing constraint for those failing paths?
Maybe you can refer to EMIF Handbook for the timing closure issue and optimizing timing:
- https://docs.altera.com/r/aigN1Vypic5yu3QMv5nT6w/XSJlBA8TdzzSQ3qEWPUIjQ
- https://docs.altera.com/r/aigN1Vypic5yu3QMv5nT6w/FN_pWR3FgpBTqD15qLBCfQ
Regards,
Adzim
