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Michal_S's avatar
Michal_S
Icon for New Contributor rankNew Contributor
2 years ago

MAX10 correct VCCIO when using LVDS

Hello Intel Community,

Can we use 3.3V VCCIO supply voltage on bank 3, where IOs are configured as differential bus - LVDS ?

Quartus pin configurator is not complaining about this situation, device is 10M16SCU169I7G.

Thank you for your replies,

Best Regards,

Michal

Generic Io

7 Replies

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    2 years ago

    Hi,
    guess you did not try to compile your design.

    Error (169026): Pin xx with I/O standard assignment Bus LVDS is incompatible with I/O bank 3. I/O standard Bus LVDS, has a VCCIO requirement of 2.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 3.3V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard.

    LVDS IO-standards can be only implemented in 2.5 V bank. If you already finished your PCB, you may try an unsupported workaround, use only 2.5 V IO standards in bank 3, although it's actually supplied by 3.3 V. LVDS performance will be reduced, you should also avoid to set higher IO-strength than supported for 3.3V to any pin in the bank.

  • Michal_S's avatar
    Michal_S
    Icon for New Contributor rankNew Contributor
    2 years ago

    Hello FvM,

    thank you very much for your reply, do you know if there is a risk of hardware failure? or is somewhere, in Intel documentation, internal structure of LVDS pins defined? I am really struggling to find it. Might be interesting to know what is behind reduced performance.

    From what we see, as we have VCCIO powered by 3.3V (unfortunately), the mid point of a LVDS bus is around 1.6V, so there seems to be ratiometric circuit depended on VCCIO -> by using 2.5V it will be 1.2V, as should be according to LVDS specification.

    Thank you

    Have a nice day

    Michal

    • FvM's avatar
      FvM
      Icon for Super Contributor rankSuper Contributor
      2 years ago

      The keyword in my previous post is "unsupported". Therefore you can't expect specifications about performance etc. You need to evaluate operation parameters on your own. Common mode output voltage, also differential voltage will be increased with 3.3 V supplied FPGA LVDS driver, most reveivers tolerate it.

  • Farabi_Altera's avatar
    Farabi_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hello,


    Yes correct, you need to follow all the requirements as published in the device datasheet. Otherwise, the functionality, performance and reliability is not guaranteed to work as expected.


    regards,

    Farabi


  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi,


    I wish to check on this issue.

    Do you need more clarification from this issue?

    If yes, please let us know so that we can support you more.


    Regards,

    Aqid


  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    I hope the previous response was sufficient to help you proceed. As we do not receive any response from you on the previous reply have been provided, please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you by replying to this thread.