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Michal_S's avatar
Michal_S
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1 year ago

MAX10 correct VCCIO when using LVDS

Hello Intel Community, Can we use 3.3V VCCIO supply voltage on bank 3, where IOs are configured as differential bus - LVDS ? Quartus pin configurator is not complaining about this situation, devic...
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Michal_S's avatar
Michal_S
Icon for New Contributor rankNew Contributor
1 year ago

Hello FvM,

thank you very much for your reply, do you know if there is a risk of hardware failure? or is somewhere, in Intel documentation, internal structure of LVDS pins defined? I am really struggling to find it. Might be interesting to know what is behind reduced performance.

From what we see, as we have VCCIO powered by 3.3V (unfortunately), the mid point of a LVDS bus is around 1.6V, so there seems to be ratiometric circuit depended on VCCIO -> by using 2.5V it will be 1.2V, as should be according to LVDS specification.

Thank you

Have a nice day

Michal

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    The keyword in my previous post is "unsupported". Therefore you can't expect specifications about performance etc. You need to evaluate operation parameters on your own. Common mode output voltage, also differential voltage will be increased with 3.3 V supplied FPGA LVDS driver, most reveivers tolerate it.