MAX10 can't accept 125 MHz clock without timing violations

I believe the ADC is the issue, but he was dropping the clock from 125MHz to 10MHz with the PLL, but since he didn't have the generated clock statements or a derive_pll_clocks statement to generate them automatically, it was assumed to be 125MHz (same as the input). Once you put in the correct clocks, the minimum pulse width errors go away.