MAX10 can't accept 125 MHz clock without timing violations

Hi.

I'm using quartus 15.0.0 64-bit on Windows 7 pro.

I'm working on a design that uses an MAX10 (10M08SAU169C8). The design calls for two clock domains.

The first is 50 MHz and the second is 125 MHz.

The 50 MHz clock domain is used for the majority of the design (well less than 50% utilization in all categories).

The 125 MHz clock feeds an instantiated PLL which is to provide a 10 MHz output on C0.

The 10 MHz output from the PLL clocks the ADC block for the temperature sense function.

When I compile the design I get timing errors in all three temperature/speed models suggesting that the restricted fmax is below 100 MHz due to a low minimum pulse width violation.

I do understand that the tool is saying I can't run over 98.something MHz.

I don't know what a low minimum pulse width violation is or what exactly the restricted FMAX means.

I thought that perhaps my other logic was the problem so I created a test design that includes only the PLL, the ADC, and a single registered output bit from the ADC.

Again, the 125 MHz goes only to the PLL which provides an 10 MHz output for the rest of the design.

When I compile the new project with or without the proper pin assignments (for my board) I still get restricted fmax low minimum pulse timing errors and a restricted fmax under 100 MHz.

I've been poking around the datasheet and can't find anything to suggest that this device can't utilize an 125 MHz clock.

I'm sure I'm doing something wrong as I'm clearly no timing expert.

Any suggestions on how to appease the timing tools?

I've attached an archive of my test project for reference.

Thanks in advance.