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Altera_Forum
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10 years ago

MAX10 can't accept 125 MHz clock without timing violations

Hi. I'm using quartus 15.0.0 64-bit on Windows 7 pro. I'm working on a design that uses an MAX10 (10M08SAU169C8). The design calls for two clock domains. The first is 50 MHz and the second is...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

This looks like it is something to due with the ADC timing requirement. I modified you design and removed the ADC and it works fine. The design looks like the clock is only going to the PLL, so I don't understand why the ADC timing is involved, but I would send your design to the mysupport area of Altera, and see if they can tell you if it's a tool issue.

I have a design that is running > 162 MHz in Max 10 but I'm not using the ADC and I'm using the dual supply part.

Pete