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Altera_Forum
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10 years ago

MAX10 can't accept 125 MHz clock without timing violations

Hi. I'm using quartus 15.0.0 64-bit on Windows 7 pro. I'm working on a design that uses an MAX10 (10M08SAU169C8). The design calls for two clock domains. The first is 50 MHz and the second is...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

The error message in this case is a bit of a red herring. The issue is you haven't defined the clock output of the PLL. You can do this by adding this command to your SDC file:

derive_pll_clocks

That will trace the input clock and create the necessary generated clock commands.

Tim

MN FAE