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Address offset from the base address when you access the component.
If you're not familiar with using Intel FPGA IP or Platform Designer (formerly known as Qsys), I'd suggest searching for documentation and training on the Avalon interface and the use of Platform Designer.
Start with the Avalon spec:
https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/manual/mnl_avalon_spec.pdf --- Quote End ---
I've created the component with Qsys - there is no base address. Any way it makes no sense - offsets in the table don't correlate with actual ports I have in the module.
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