Forum Discussion
Altera_Forum
Honored Contributor
7 years agoHow do I map the module signals?
component altera_dual_config is
port (
avmm_rcv_address : in std_logic_vector(2 downto 0) := (others => '0'); -- avalon.address
avmm_rcv_read : in std_logic := '0'; -- .read
avmm_rcv_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
avmm_rcv_write : in std_logic := '0'; -- .write
avmm_rcv_readdata : out std_logic_vector(31 downto 0); -- .readdata
clk : in std_logic := '0'; -- clk.clk
nreset : in std_logic := '0' -- nreset.reset_n
);
end component;
Especially avmm_rcv_address : in std_logic_vector(2 downto 0) - what is this address? why 3 lines wide? why there is no tutorial about Altera Dual Configuration module?