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Altera_Forum
Honored Contributor
Honored ContributorMAX10 and Flash Update module
I created Flash Update module with Qsys
onchip_flash_0 : component altera_onchip_flash
generic map (
INIT_FILENAME => "",
INIT_FILENAME_SIM => "",
DEVICE_FAMILY => "MAX 10",
PART_NAME => "10M50DAF484C7G",
DEVICE_ID => "50",
SECTOR1_START_ADDR => 0,
SECTOR1_END_ADDR => 8191,
SECTOR2_START_ADDR => 8192,
SECTOR2_END_ADDR => 16383,
SECTOR3_START_ADDR => 16384,
SECTOR3_END_ADDR => 114687,
SECTOR4_START_ADDR => 114688,
SECTOR4_END_ADDR => 188415,
SECTOR5_START_ADDR => 188416,
SECTOR5_END_ADDR => 360447,
MIN_VALID_ADDR => 0,
MAX_VALID_ADDR => 360447,
MIN_UFM_VALID_ADDR => 0,
MAX_UFM_VALID_ADDR => 16383,
SECTOR1_MAP => 1,
SECTOR2_MAP => 2,
SECTOR3_MAP => 3,
SECTOR4_MAP => 4,
SECTOR5_MAP => 5,
ADDR_RANGE1_END_ADDR => 360447,
ADDR_RANGE1_OFFSET => 2048,
ADDR_RANGE2_OFFSET => 0,
AVMM_DATA_ADDR_WIDTH => 19,
AVMM_DATA_DATA_WIDTH => 32,
AVMM_DATA_BURSTCOUNT_WIDTH => 4,
SECTOR_READ_PROTECTION_MODE => 0,
FLASH_SEQ_READ_DATA_COUNT => 4,
FLASH_ADDR_ALIGNMENT_BITS => 2,
FLASH_READ_CYCLE_MAX_INDEX => 5,
FLASH_RESET_CYCLE_MAX_INDEX => 7,
FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX => 36,
FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX => 10500000,
FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX => 9150,
PARALLEL_MODE => true,
READ_AND_WRITE_MODE => true,
WRAPPING_BURST_MODE => false,
IS_DUAL_BOOT => "False",
IS_ERAM_SKIP => "True",
IS_COMPRESSED_IMAGE => "True"
)
port map (
clock => clock, -- clk.clk
reset_n => reset_n, -- nreset.reset_n
avmm_data_addr => avmm_data_addr, -- data.address
avmm_data_read => avmm_data_read, -- .read
avmm_data_writedata => avmm_data_writedata, -- .writedata
avmm_data_write => avmm_data_write, -- .write
avmm_data_readdata => avmm_data_readdata, -- .readdata
avmm_data_waitrequest => avmm_data_waitrequest, -- .waitrequest
avmm_data_readdatavalid => avmm_data_readdatavalid, -- .readdatavalid
avmm_data_burstcount => avmm_data_burstcount, -- .burstcount
avmm_csr_addr => avmm_csr_addr, -- csr.address
avmm_csr_read => avmm_csr_read, -- .read
avmm_csr_writedata => avmm_csr_writedata, -- .writedata
avmm_csr_write => avmm_csr_write, -- .write
avmm_csr_readdata => avmm_csr_readdata -- .readdata
);
IS_DUAL_BOOT => "True",
IS_ERAM_SKIP => "True",
IS_COMPRESSED_IMAGE => "True"
IS_DUAL_BOOT => "False",
IS_ERAM_SKIP => "True",
IS_COMPRESSED_IMAGE => "True"
IS_DUAL_BOOT => "True",
IS_ERAM_SKIP => "True",
IS_COMPRESSED_IMAGE => "True"
14 Replies
Altera_ForumHi,
Have you set the correct parameter setting of Nios ll and on-chip ram? Delete the incremental_db and db folder and recheck. Refer the document for steps. http://caxapa.ru/thumbs/592124/an730.pdf Let me know if this has helped resolve the issue you are facing or if you need any further assistance. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)- Altera_Forum--- Quote Start --- Hi, Have you set the correct parameter setting of Nios ll and on-chip ram? Delete the incremental_db and db folder and recheck. Refer the document for steps. http://caxapa.ru/thumbs/592124/an730.pdf Let me know if this has helped resolve the issue you are facing or if you need any further assistance. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation) --- Quote End --- I don't have NiosII in my project. It's QSYS generated core. I go Tools->IP Catalog->Library->Basic Functions->On Chip Memory->Altera On-Chip Flash.https://alteraforum.com/forum/attachment.php?attachmentid=15108&stc=1 I deleted the incremental_db and db folder - it didn't help.
- Altera_Forum
As it says, you need to have the RSU block in your design to use dual compressed images. See these online trainings:
https://www.altera.com/support/training/course/omaxrsu101.html https://www.altera.com/support/training/course/omaxrsu102.html - Altera_Forum--- Quote Start --- As it says, you need to have the RSU block in your design to use dual compressed images. See these online trainings: https://www.altera.com/support/training/course/omaxrsu101.html https://www.altera.com/support/training/course/omaxrsu102.html --- Quote End --- I see. Thank you. Well...I created Altera On-Chip Flash module and Altera Dual Configuration module.
But I completely didn't understand how to connect between these two modules.component flash_update is port ( clock : in std_logic := '0'; -- clk.clk avmm_csr_addr : in std_logic := '0'; -- csr.address avmm_csr_read : in std_logic := '0'; -- .read avmm_csr_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata avmm_csr_write : in std_logic := '0'; -- .write avmm_csr_readdata : out std_logic_vector(31 downto 0); -- .readdata avmm_data_addr : in std_logic_vector(18 downto 0) := (others => '0'); -- data.address avmm_data_read : in std_logic := '0'; -- .read avmm_data_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata avmm_data_write : in std_logic := '0'; -- .write avmm_data_readdata : out std_logic_vector(31 downto 0); -- .readdata avmm_data_waitrequest : out std_logic; -- .waitrequest avmm_data_readdatavalid : out std_logic; -- .readdatavalid avmm_data_burstcount : in std_logic_vector(3 downto 0) := (others => '0'); -- .burstcount reset_n : in std_logic := '0' -- nreset.reset_n ); end component; component altera_dual_config is port ( avmm_rcv_address : in std_logic_vector(2 downto 0) := (others => '0'); -- avalon.address avmm_rcv_read : in std_logic := '0'; -- .read avmm_rcv_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata avmm_rcv_write : in std_logic := '0'; -- .write avmm_rcv_readdata : out std_logic_vector(31 downto 0); -- .readdata clk : in std_logic := '0'; -- clk.clk nreset : in std_logic := '0' -- nreset.reset_n ); end component; - Altera_Forum
Hi,
For a complete solution on dual configuration with reference design refer below link. https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/an/an741.pdf Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation) - Altera_Forum
Did you watch part 1 of the training? It goes through everything you need to do. You need a control mechanism, like Nios, to do this.
- Altera_Forum
How do I map the module signals?
Especially avmm_rcv_address : in std_logic_vector(2 downto 0) - what is this address? why 3 lines wide? why there is no tutorial about Altera Dual Configuration module?component altera_dual_config is port ( avmm_rcv_address : in std_logic_vector(2 downto 0) := (others => '0'); -- avalon.address avmm_rcv_read : in std_logic := '0'; -- .read avmm_rcv_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata avmm_rcv_write : in std_logic := '0'; -- .write avmm_rcv_readdata : out std_logic_vector(31 downto 0); -- .readdata clk : in std_logic := '0'; -- clk.clk nreset : in std_logic := '0' -- nreset.reset_n ); end component; - Altera_Forum
- Altera_Forum--- Quote Start --- All documented here: https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/max-10/ug_m10_config.pdf --- Quote End --- I have read this document. No explanation about the module. There is only a picture on the 2-16 page.
- Altera_Forum
Look at the end of the document. The IP and its addressable locations are described.
