--- Quote Start ---
As it says, you need to have the RSU block in your design to use dual compressed images. See these online trainings:
https://www.altera.com/support/training/course/omaxrsu101.html https://www.altera.com/support/training/course/omaxrsu102.html --- Quote End ---
I see. Thank you.
Well...I created Altera On-Chip Flash module and Altera Dual Configuration module.
component flash_update is
port (
clock : in std_logic := '0'; -- clk.clk
avmm_csr_addr : in std_logic := '0'; -- csr.address
avmm_csr_read : in std_logic := '0'; -- .read
avmm_csr_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
avmm_csr_write : in std_logic := '0'; -- .write
avmm_csr_readdata : out std_logic_vector(31 downto 0); -- .readdata
avmm_data_addr : in std_logic_vector(18 downto 0) := (others => '0'); -- data.address
avmm_data_read : in std_logic := '0'; -- .read
avmm_data_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
avmm_data_write : in std_logic := '0'; -- .write
avmm_data_readdata : out std_logic_vector(31 downto 0); -- .readdata
avmm_data_waitrequest : out std_logic; -- .waitrequest
avmm_data_readdatavalid : out std_logic; -- .readdatavalid
avmm_data_burstcount : in std_logic_vector(3 downto 0) := (others => '0'); -- .burstcount
reset_n : in std_logic := '0' -- nreset.reset_n
);
end component;
component altera_dual_config is
port (
avmm_rcv_address : in std_logic_vector(2 downto 0) := (others => '0'); -- avalon.address
avmm_rcv_read : in std_logic := '0'; -- .read
avmm_rcv_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
avmm_rcv_write : in std_logic := '0'; -- .write
avmm_rcv_readdata : out std_logic_vector(31 downto 0); -- .readdata
clk : in std_logic := '0'; -- clk.clk
nreset : in std_logic := '0' -- nreset.reset_n
);
end component;
But I completely didn't understand how to connect between these two modules.
Honored Contributor
