Honored Contributor
Honored ContributorI presume the EPE estimation is correct. Your design should be well with a linear regulator.
As mentioned in the pin connection guidelines, VCCA bypassing is particularly relevant for PLL jitter. On the other hand, how much simultaneous switching noise is generated by your FPGA? Depends on the number of active outputs, toggle rate and load. If your design doesn't use PLLs or in jitter sensitive applications, a single 3.3V plane can be well acceptable. Similar problem about number and placement of bypass capacitors. If you did already decide for double side assembly, a bypass capacitor for each power pin is easy to implement, also VCCA ferrite filters. You can do some experiments by providing the components and omitting it later.
