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Honored Contributor
Honored ContributorMax10 10M08SAU169 Layout, PDN tool required?
Hello, I have a 4 layer board with Max10 10M08SAU169 (Single Power supply, not using the ADC) device. This is a UBGA package with 0.8mm pitch and I am using several vias, in-between the v...
Altera_ForumHonored Contributor
Honored ContributorI presume the EPE estimation is correct. Your design should be well with a linear regulator.
As mentioned in the pin connection guidelines, VCCA bypassing is particularly relevant for PLL jitter. On the other hand, how much simultaneous switching noise is generated by your FPGA? Depends on the number of active outputs, toggle rate and load. If your design doesn't use PLLs or in jitter sensitive applications, a single 3.3V plane can be well acceptable. Similar problem about number and placement of bypass capacitors. If you did already decide for double side assembly, a bypass capacitor for each power pin is easy to implement, also VCCA ferrite filters. You can do some experiments by providing the components and omitting it later.
