Max10 - Are there internal weak pull-ups on the pins during flash load.

I am working on a new design for the Max 10 10M25SCE144A7G FPGA. I would like to confirm that the device implements an internal weak pull-up on all tri-state pins during flash load of the FPGA code.

This has been my experience on other Altera FPGA’s but I can’t seem to find conformation in the datasheets for the Max 10 family. I know you can configure the use of an internal weak pull-up after load but I need to be sure the weak pull-ups are applied prior to load to be sure I know the initial state of the pins connected to my external logic during power-up.