Forum Discussion
GLB
New Contributor
7 years agoMax10 - Are there internal weak pull-ups on the pins during flash load.
I am working on a new design for the Max 10 10M25SCE144A7G FPGA. I would like to confirm that the device implements an internal weak pull-up on all tri-state pins during flash load of the FPGA code. ...
Rahul_S_Intel1
Frequent Contributor
7 years agoHi ,
Kindly find the flow chart for the I/O states before ,during and after configuration
Page no:28
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_config.pdf