Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

max v ports at power upMany thanks.

Hi, I'm using a MAXV (5M160ZE64I5N) device and I'm having problems with Output lines going high during the 'Boot' cycle of the CPLD.

Looking at the MAX V handbook, during the 'Boot' period the device turns on the 'Weak Pullup' until it's ready to run. This is causing me some problems as one of the lines MUST be low during power up, and must not glitch.

Obviously a pull down resistor will work, but as the Pullup is 5K-25K any pull down will only limit the peak voltage during power up, but it won't stop it happening.

Is there a way of stopping this weak pullup (I don't mind the tristate) happening during the 'Boot' process?

Thanks

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    No. There is no way of stopping this weak pull-up during boot - i.e. during tCONFIG.

    You mention a pull-down resistor. Is that not sufficient? I'd suggest a 1kR pull-down is likely to overcome any issue you're seeing.

    Cheers,

    Alex
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    --- Quote Start ---

    You mention a pull-down resistor. Is that not sufficient? I'd suggest a 1kR pull-down is likely to overcome any issue you're seeing.

    --- Quote End ---

    No the pull down will not work in this situation. It's a reset line to a Intel Chipset which must not glitch during power up. The pull down only 'limits' the voltage spike, it doesn't get rid of it completely.

    The only option here for me is to put external pulldown and insert a Schmitt Buffer to overcome the voltage spike.

    One would have hoped that the CPLD could have done that for me.... as it's logic, but obviously it can't. I just see that as a bit backwards as not all people would like a Positive Blip at startup especcialy on a CPU reset line!

    Many thanks.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    The unprogrammed pull-up resistor current is, worst case, 300uA. With a 1kR pull-down you're looking at a peak voltage 'spike' of 0.3V. Are you sure you're buffer isn't going to generate anything worse than that at power up?

    If you really don't want anything like that voltage appearing on the CPU reset line, then it must have a pull down on the CPU reset pin. Behind that I suggest you use something much simpler than a buffer - a pass transistor, or more likely a MOSFET. The pass FET's gate is connected to a CPLD output, as is it's 'input' (drain). The gate's pull down resistor will ensure it doesn't switch on (for the same reason as stated above), something it would need to do in order to expose your CPU reset to any positive voltage. Once the CPLD is booted it drives the gate of the FET on - thus switching 'on' the pass path - and controls the CPU reset through the drain-source path.

    Cheers,

    Alex