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Altera_Forum's avatar
Altera_Forum
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10 years ago

max v ports at power upMany thanks.

Hi, I'm using a MAXV (5M160ZE64I5N) device and I'm having problems with Output lines going high during the 'Boot' cycle of the CPLD. Looking at the MAX V handbook, during the 'Boot' period the dev...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

The unprogrammed pull-up resistor current is, worst case, 300uA. With a 1kR pull-down you're looking at a peak voltage 'spike' of 0.3V. Are you sure you're buffer isn't going to generate anything worse than that at power up?

If you really don't want anything like that voltage appearing on the CPU reset line, then it must have a pull down on the CPU reset pin. Behind that I suggest you use something much simpler than a buffer - a pass transistor, or more likely a MOSFET. The pass FET's gate is connected to a CPLD output, as is it's 'input' (drain). The gate's pull down resistor will ensure it doesn't switch on (for the same reason as stated above), something it would need to do in order to expose your CPU reset to any positive voltage. Once the CPLD is booted it drives the gate of the FET on - thus switching 'on' the pass path - and controls the CPU reset through the drain-source path.

Cheers,

Alex