Max V output pin in a disconnected mode on logic 1

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Do I need any passive external components to make this work?

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No, you just need to describe it the way you want. For example, in VHDL the code for a tri-state buffer with an active-low output-enable is

output_pin <= 'Z' when (output_enableN = '1') else '0';

This describes a tri-state buffer with a zero on its input. When you enable the buffer it drives the output pin low, when you disable the buffer, the output pin is tristated.

You can do something similar with a buffer component in the schematic editor, or in Verilog HDL.

Cheers,

Dave