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Hi,
all Altera devices have weak pull-ups, which are enabled until the device enters user mode (i.e. during configuration, etc.). My understanding is that these are also applied while the CPLD is not programmed yet, at least I could not find anything contrary in the manuals.
The spec for the MAX V is not as clear as e.g. for Cyclone devices, but as far as I understood it, the weak pull-up resistor depends on the applied I/O voltage, and it can be as low as 5 kOhm.
So I'd say as long as all your CPU signals are properly driven (and you don't use any fancy open-emitter outputs), the CPLD should not interfere with the CPU.
Best regards,
GooGooCluster
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Thank you GooGooCluster.
Shony
Honored Contributor
