MAX V DEV Board

library ieee;
use ieee.std_logic_1164.all;

entity voltinout is
    port(
        inpinvolt  : in  std_logic;
        outpinvolt : out std_logic
    );
end entity voltinout;

architecture Behavior of voltinout is
begin
        outpinvolt <= inpinvolt;
end architecture behavior;

I used pin assignment to specify inpinvolt to J6.1(P2) and outpinvolt to J6.2(M4). My code compiled and in the RTL viewer it shows a direct connection from input to output. 

I used a 3.3V supply and connect it with the input in J6.1 to GND but the output at J6.2 shows zero with a multimeter.