Forum Discussion
New ContributorMAX V DEV Board
Hi Abedin,
I wanted to follow up on this case to check if you have any further questions or concerns. Please feel free to reach out if there's anything you'd like us to assist you with.
Regards,
Fakhrul
New Contributorlibrary ieee;
use ieee.std_logic_1164.all;
entity voltinout is
port(
inpinvolt : in std_logic;
outpinvolt : out std_logic
);
end entity voltinout;
architecture Behavior of voltinout is
begin
outpinvolt <= inpinvolt;
end architecture behavior;
I used pin assignment to specify inpinvolt to J6.1(P2) and outpinvolt to J6.2(M4). My code compiled and in the RTL viewer it shows a direct connection from input to output.
I used a 3.3V supply and connect it with the input in J6.1 to GND but the output at J6.2 shows zero with a multimeter.
Regular ContributorHi Abedin,
Your VHDL looks fine. The issue is likely board setup or pin configuration. Check these:
Pin mapping – Confirm J6.1 and J6.2 are real GPIO pins, not power or ground.
Bank voltage – The MAX V device uses separate VCCIO for I/O banks. Make sure the jumper for your bank is set to 3.3 V.
I/O standard – In Quartus, set both pins to 3.3 V LVTTL/LVCMOS to match VCCIO.
Avoid special pins – Do not use pins tied to LEDs, buttons, or dedicated signals.
Quick test – Map input to a push button and output to an LED to confirm the design works.
Wiring – Double-check header orientation and GND connection.
Let me know if you need further help.
Regards,
Fakhrul
- abedin
Thanks for your email. The board J6 and J7 I/O connector pins get power from 3.3V Conn pin which has to be populated and powered externally. After doing that my code works. Unfortunately, it was not intuitive from the reference guide.
