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Ian_Gibb's avatar
Ian_Gibb
Icon for New Contributor rankNew Contributor
4 years ago
Solved

MAX 10 PLL input and output clocks warnings

Device Max10M40DA256 Nios + SDRAM + application IP on avalon bus I get warnings on the PLL clocks about the input clock to PLL inclock[0] and an output clock to the SDRAM CK input. Only one PLL i...
  • Ian_Gibb's avatar
    Ian_Gibb
    4 years ago

    Hi Ash,

    Thanks for this, thats all good now. I also found i had declared the input clock as a global clock which it did not like ... i assume because it no longer exclusive to the PLL input. With that and your notes above i no longer get these warnings.

    Many thanks for your help.

    Ian

Ash_R_Intel's avatar
Ash_R_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi Ian,

Though you are using the CLK0 pin, the PLL instance location also matters here. You will not see this warning if CLK0 is driving either PLL1 or PLL3. If PLL2 or PLL4 got instantiated, then you will see this warning. Please confirm which PLL has got instantiated in your design.

You may constraint the SDRAM and NIOS IP placement such that the dedicated PLL gets instantiated.


Regards.


  • Ian_Gibb's avatar
    Ian_Gibb
    Icon for New Contributor rankNew Contributor
    4 years ago

    Hi Ash,

    Thanks for your comments, which make sense. I was kind of thinking that the compiler would make a logical decision on allocating the PLL from the i/p clock source ... maybe.

    Can you clarify how to define which PLL to use when the instantiation is done, i am struggling to find this setting ?

    I have fixed the SDRAM clock output by instantiating the PLL outside the NIOS IP and passing through a ALTCLKCNTRL to output the SDRAM from pll_c0 to the dedicated PLLOUT pin, PLL_L_CLKOUTp

    So I need to use the associated input clock to that PLL to fix the other warning.. But the PLL_L_CLKOUTp are named B, L, R, T rather than 1,2,3,4 ?! (from the device pinout files)

    How do i know which is which?

    Regards

    Ian