Matrix Multiplication optimization

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I highly suggest you get a VHDL textbook and read up on how to write VHDL for digital designs. The current code just looks like you're trying to write some software inside a single process. This will not give a very efficient design, as there is no pipelining, so you will only be able to run the design at a very low clock speed (low FMax - max frequency).

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Thanks for your suggestion. I will look for VHDL book. Can you please explain in a sentence or two about pipelining...what is it??? and why use of signal is much appreciated than use of variables????

Pipelining is the chain of registers that are inserted into your algorithm to reduce the logic between registers. It increases the latency, but massively increases the FMax. Latency is usually not important, it's the throughput that counts (and throughput increases with clock speed).

As for signals vs variables: signals are only updated when a process suspends - so in a clocked proecss every signal assignment will become a register. Variables are updated immediately, so the logic that is produces depends on the order of the assignments in the code.

There is nothing you can do with variables that you cannot do with signals. And as variables can be more unpredictable, usings signals is far safer for a beginner.

But, I highly recommend you take a step back. Do you have a drawing of how this algorithm will look on hardware? one that you drew before you wrote any code? HDL is a hardware description language - if you dont know what hardware you want, how do you expect to describe it?