--- Quote Start ---
I highly suggest you get a VHDL textbook and read up on how to write VHDL for digital designs. The current code just looks like you're trying to write some software inside a single process. This will not give a very efficient design, as there is no pipelining, so you will only be able to run the design at a very low clock speed (low FMax - max frequency).
--- Quote End ---
Thanks for your suggestion. I will look for VHDL book. Can you please explain in a sentence or two about pipelining...what is it??? and why use of signal is much appreciated than use of variables????
Honored Contributor
