Thanks alot saurabhraj
I want to explain a bit on what i have to do. I am using a MATLAB code for SPIHT image compression and i have individual files for each step, since SPIHT proceeds in several phases Dominant pass, Subordinate pass etc.. Now i was thinking if i could translate each file in to an individual module of Verilog.
The links you sent me suggested converting to C and then to Verilog. It seems fairly undertandable to me, sadly I have zero experinece with C and do you think this will slow down the code? As in two steps will give significant delays?
Thankyou