Matching Cyclone III Signal Impedance to 65Ohm cPCI Traces

If your cPCI interface device is close to the cPCI connector, you don't need to have 65-Ohms on your PCB. Its more important that you have 10-ohm stub terminations, or if you want hot-swap cPCI use bus switches near the cPCI connector.

For example, here's a board that uses a PowerPC for a hot-swappable cPCI interface and Stratix II FPGAs:

http://www.ovro.caltech.edu/~dwh/carma_board/ (http://www.ovro.caltech.edu/%7edwh/carma_board/)

http://www.ovro.caltech.edu/~dwh/carma_board/gda06rb004_carma_v0.87_dec03.pdf (http://www.ovro.caltech.edu/%7edwh/carma_board/gda06rb004_carma_v0.87_dec03.pdf)

and here's one that uses a PLX9054 for a regular cPCI interface:

http://www.ovro.caltech.edu/~dwh/correlator/pdf/correlator_sch_rev_c1.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/correlator_sch_rev_c1.pdf)

Cheers,

Dave

One other thing; the CARMA board link that I posted uses bus switches on the cPCI interface to implement hot-swap and a 5V/3.3V universal cPCI interface. Its pretty common to still have 5V cPCI backplanes, and the Cyclone III device is probably not 5V tolerant. If you are building a product, then a universal cPCI interface would be a good thing.

The web link I sent has the PCB layout files (Cadence Allegro), so you can look at the layout with Cadence's free viewer. The routing between the bus switches and your Cyclone III will be much simpler than the PowerPC design. I'd recommend copying the implementation on that board.

Just ask if you have questions.

Cheers,

Dave

Dave,

Thank you very much for your response and help! I will look over the links that you have given me and will make sure to ask any questions should they arise.

I have made sure to include the 10 Ohm stub terminations in my design and will not be implementing hot-swap capability as this board will be part of a closed system. Just to clarify, typical 50 Ohm PCB traces to the Cyclone III from the J1 connector (as I'll be working with 32-bit cPCI) will be acceptable as long as I maintain short traces (which I think the maximum trace length by spec of 1.5" should then suffice since my system will be running at 33MHz)?

-Jim

Hi Jim,

Your design should work fine at 33MHz. Length matching won't be an issue at 33MHz, just route the traces via the most convenient path, and then P&R the FPGA PCI interface to double-check there are no pin assignment issues (rules violations).

I would recommend having a separate oscillator on the board so that your FPGA logic can operate independently of the 33MHz PCI clock being present or not. Even if this oscillator is only used during initial board bring-up. Make sure you have a footprint on the PCB, or a header to route a clock onto the board.

The 33MHz clock is never actually 33MHz, and sometimes you need to know the frequency. For example, on the CARMA board, the PowerPC runs Linux, and the PowerPC PLLs use the PCI clock as their reference. To get Linux time working correctly, we had to count the 33MHz clock using a known-frequency oscillator, and then let Linux know the PowerPC core clock frequency based on the measured 33MHz value (times the PLL multiplication factor).

Who knew :)

Cheers,

Dave

Dave,

Thank you. It's good to know that I shouldn't need to be too concerned about length matching. In talking with my manager, we are looking to make sure this board works in a cPCI system rather than looking to call this board cPCI-compliant which, in turn, removes a lot of worry as well.

Due to wanting to keep the non-PCI FPGA logic separated as much as possible from the PCI portion, I had already put a separate oscillator in my design...I had not thought about using it to verify the incoming PCI frequency, though. I like that idea.

-Jim