Honored Contributor
Honored ContributorHi Jim,
Your design should work fine at 33MHz. Length matching won't be an issue at 33MHz, just route the traces via the most convenient path, and then P&R the FPGA PCI interface to double-check there are no pin assignment issues (rules violations). I would recommend having a separate oscillator on the board so that your FPGA logic can operate independently of the 33MHz PCI clock being present or not. Even if this oscillator is only used during initial board bring-up. Make sure you have a footprint on the PCB, or a header to route a clock onto the board. The 33MHz clock is never actually 33MHz, and sometimes you need to know the frequency. For example, on the CARMA board, the PowerPC runs Linux, and the PowerPC PLLs use the PCI clock as their reference. To get Linux time working correctly, we had to count the 33MHz clock using a known-frequency oscillator, and then let Linux know the PowerPC core clock frequency based on the measured 33MHz value (times the PLL multiplication factor). Who knew :) Cheers, Dave
