Marvell 88E1111 PHY on DE2-115

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We're a couple of students doing our main project on this board, a design with no softcores.

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What is the point of not using an IP core that is already debugged and tested?

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we've been struggling with it for weeks :(

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Which is why you should use a working IP core.

If your task is to write an interface to the PHY, then I would recommend using a working IP core as a reference to see what it does to access the device. For example, Altera have a TSE core. Use it along with SignalTap II to trace what is going on in a working design.

If your project involves just using the TSE core, then get your professor to request the license for the IP core via the University Program, and then use the board to do something more interesting :)

Cheers,

Dave

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What is the point of not using an IP core that is already debugged and tested?

Which is why you should use a working IP core.

If your task is to write an interface to the PHY, then I would recommend using a working IP core as a reference to see what it does to access the device. For example, Altera have a TSE core. Use it along with SignalTap II to trace what is going on in a working design.

If your project involves just using the TSE core, then get your professor to request the license for the IP core via the University Program, and then use the board to do something more interesting :)

Cheers,

Dave

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Well, the MDIO and ETH FSM checks out just fine. Just now set some states it in a loop, wired SW and LEDR into reading and writing off the basic management register. PHY responds and reports appropriately.

We wanted to learn *VHDL*, no cores, big fun that at least THAT part of it is ok! :)

Thanks for the tip about signaltapping into an existing design btw!

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We wanted to learn *VHDL*, no cores

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In that case, start with something that you can get the whole data sheet to, eg., an asynchronous SRAM or Flash interface, an SSRAM interface, an SDRAM controller, etc. Marvell is a pain to get datasheets from.

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Thanks for the tip about signaltapping into an existing design btw!

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Its also very useful to trying to understand what an Altera IP core does in hardware. Sometimes the documentation can be a little 'light' on details.

Cheers,

Dave

Some time spent SignalTapping saved my day here!

It revealed the HIGH-LOW-HIGH-HIGH signal on the 4 RGMII data lines did fluctuate a bit, it's just not visible if displayed on LED's.

A signaltap with RX_CLK as clock and DV as trigger; it's actually Ethernet...

http://s17.postimage.org/6pmiz1sr3/signaltap_ethernet_data_100_Mbps_link.png

:)

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Indeed. I guess one of the LED's blinking off for a few nanoseconds is kind of hard to see, LOL.

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Yeah, I think what you are supposed to do is have an LED blinking circuit that detects an edge, and then turns on for a 100ms, so you can at least see it :)