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What is the point of not using an IP core that is already debugged and tested?
Which is why you should use a working IP core.
If your task is to write an interface to the PHY, then I would recommend using a working IP core as a reference to see what it does to access the device. For example, Altera have a TSE core. Use it along with SignalTap II to trace what is going on in a working design.
If your project involves just using the TSE core, then get your professor to request the license for the IP core via the University Program, and then use the board to do something more interesting :)
Cheers,
Dave
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Well, the MDIO and ETH FSM checks out just fine. Just now set some states it in a loop, wired SW and LEDR into reading and writing off the basic management register. PHY responds and reports appropriately.
We wanted to learn *VHDL*, no cores, big fun that at least THAT part of it is ok! :)
Thanks for the tip about signaltapping into an existing design btw!
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