Mapping a basic UART project to the HPS_UART pins
Hi,
I am currently working working on a project for a class that I am TAing and was asked to add the ability to send and receive data between the DE1-SoC board and a host computer.
I have built a project following this video here:
https://www.youtube.com/watch?v=fMmcSpgOtJ4
but when I set up the pin assignments for the HPS_UART_RX and HPS_UART_TX pins I get the following errors:
Error (14566): The Fitter cannot place 2 periphery component(s) due to conflicts with existing constraints (2 pin(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (175020): The Fitter cannot place logic pin in region (79, 81) to (79, 81), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info (14596): Information about the failing component(s):
Info (175028): The pin name(s): UART_TXD
Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Error (184016): There were not enough single-ended output pin locations available (1 location affected)
Info (175029): C25
Info (175015): The I/O pad UART_TXD is constrained to the location PIN_C25 due to: User Location Constraints (PIN_C25)
Info (14709): The constrained I/O pad is contained within this pin
and the same for UART_RXD on PIN_B25
any help on how to resolve this issue would be appreciated
Cheers