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Altera_Forum's avatar
Altera_Forum
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18 years ago

M4K memory problem in cyclone II 35672c6 device,

Dear Frineds,

when i am targetting a simple dual port memory for m4k, quartus 7.1 gives this error,

if target for LC's no problem, but i need more logic for my design, so targetting M4k is important, any help reagarding this is appreciated, i tried many data sheets and errta sheets.

regards

baba

---------------

Quartus II

---------------------------

Full Compilation was NOT successful (16 errors, 132 warnings)

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확인

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Info: Instantiated megafunction "sld_hub:sld_hub_inst" with the following parameter:

Info: Parameter "SLD_HUB_IP_VERSION" = "1"

Info: Parameter "SLD_HUB_IP_MINOR_VERSION" = "3"

Info: Parameter "SLD_COMMON_IP_VERSION" = "0"

Info: Parameter "N_NODES" = "2"

Info: Parameter "N_SEL_BITS" = "2"

Info: Parameter "N_NODE_IR_BITS" = "5"

Info: Parameter "NODE_INFO" = "0000110000000000011011100000000000010001000100000100011000000000"

Info: Parameter "COMPILATION_MODE" = "1"

Info: Parameter "DEVICE_FAMILY" = "Cyclone II"

Error: WYSIWYG RAM primitive "ram_block2a0" must have Port A, Address port or parameter specified

Error: WYSIWYG RAM primitive "ram_block2a0" must have Port B, Address port or parameter specified

Error: WYSIWYG RAM primitive "ram_block2a1" must have Port A, Address port or parameter specified

Error: WYSIWYG RAM primitive "ram_block2a1" must have Port B, Address port or parameter specified

Error: WYSIWYG RAM primitive "ram_block2a2" must have Port A, Address port or parameter specified

Error: WYSIWYG RAM primitive "ram_block2a2" must have Port B, Address port or parameter specified

Error: WYSIWYG RAM primitive "ram_block2a3" must have Port A, Address port or parameter specified

Error: WYSIWYG RAM primitive "ram_block2a3" must have Port B, Address port or parameter specified

Error: WYSIWYG RAM primitive "ram_block2a4" must have Port A, Address port or parameter specified

Error: WYSIWYG RAM primitive "ram_block2a4" must have Port B, Address port or parameter specified

Error: WYSIWYG RAM primitive "ram_block2a5" must have Port A, Address port or parameter specified

Error: WYSIWYG RAM primitive "ram_block2a5" must have Port B, Address port or parameter specified

Error: WYSIWYG RAM primitive "ram_block2a6" must have Port A, Address port or parameter specified

Error: WYSIWYG RAM primitive "ram_block2a6" must have Port B, Address port or parameter specified

Error: WYSIWYG RAM primitive "ram_block2a7" must have Port A, Address port or parameter specified

Error: WYSIWYG RAM primitive "ram_block2a7" must have Port B, Address port or parameter specified

7 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Did you use the megawizard and then instantiate the output file? Are you synthesizing in Quartus? The error message basically says its not finding a required parameter, so how are you passing this parameter in? (You don't manually do this, the megawizard adds this and then you usually instantiate that file.)

  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Has there been a resolution to this problem? I'm getting the same error. I've just used the megawizard to create a Verilog module and call that in other modules and it gives me this error.

  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    It sounds like a megafunction is being instantiated with incorrect(or missing) parameters. Without any extra information, including the file, it's impossible to tell. If you want someone to look at it specifically, I would file an SR.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Hello Altera Gurus,

    I´ve got the same problem as above... my first post here and I´ve already used the search and won´t open a new thread. Isn´t that amazing?

    Sorry... to the point:

    I´ve used a reference design for CycloneII NiosII Devboard and entered SOPC Builder. Then I wrote my wrapper to connect my pipeline like this:

    Avalon MM -> ST -> Pipeline -> Avalon ST -> MM

    Then I´ve handled some errors and resolved problems. The system generation was successfull and I´ve updated the block in the .bdf file. Reconnected some wires and started compilation...

    After about 900 Warnings the errors occured: 

    
Error: WYSIWYG RAM primitive "ram_block2a0" must have Port A, Address port or parameter specified
Error: WYSIWYG RAM primitive "ram_block2a0" must have Port B, Address port or parameter specified
Error: WYSIWYG RAM primitive "ram_block2a1" must have Port A, Address port or parameter specified
    The double click on one of this messages shows the following section: 

    
VARIABLE 
    ram_block2a0 : cycloneii_ram_block
        WITH (
            CONNECTIVITY_CHECKING = "OFF",
            LOGICAL_RAM_NAME = "ALTSYNCRAM",
            MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
            OPERATION_MODE = "bidir_dual_port",
            PORT_A_ADDRESS_WIDTH = 11,
            PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
            PORT_A_BYTE_SIZE = 1,
            PORT_A_DATA_WIDTH = 1,
            PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
            PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
            PORT_A_FIRST_ADDRESS = 0,
            PORT_A_FIRST_BIT_NUMBER = 0,
            PORT_A_LAST_ADDRESS = 2047,
            PORT_A_LOGICAL_RAM_DEPTH = 2048,
            PORT_A_LOGICAL_RAM_WIDTH = 32,
            PORT_B_ADDRESS_CLOCK = "clock1",
            PORT_B_ADDRESS_WIDTH = 11,
            PORT_B_BYTE_ENABLE_CLOCK = "clock1",
            PORT_B_BYTE_ENABLE_MASK_WIDTH = 1,
            PORT_B_BYTE_SIZE = 1,
            PORT_B_DATA_IN_CLOCK = "clock1",
            PORT_B_DATA_WIDTH = 1,
            PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
            PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
            PORT_B_FIRST_ADDRESS = 0,
            PORT_B_FIRST_BIT_NUMBER = 0,
            PORT_B_LAST_ADDRESS = 2047,
            PORT_B_LOGICAL_RAM_DEPTH = 2048,
            PORT_B_LOGICAL_RAM_WIDTH = 32,
            PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
            POWER_UP_UNINITIALIZED = "false",
            RAM_BLOCK_TYPE = "AUTO"
        );
    ram_block2a1 : cycloneii_ram_block
        WITH (
            CONNECTIVITY_CHECKING = "OFF",
            LOGICAL_RAM_NAME = "ALTSYNCRAM",
            MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
            OPERATION_MODE = "bidir_dual_port",
            PORT_A_ADDRESS_WIDTH = 11,
            PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
            PORT_A_BYTE_SIZE = 1,
            PORT_A_DATA_WIDTH = 1,
            PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
            PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
            PORT_A_FIRST_ADDRESS = 0,
            PORT_A_FIRST_BIT_NUMBER = 1,
            PORT_A_LAST_ADDRESS = 2047,
            PORT_A_LOGICAL_RAM_DEPTH = 2048,
            PORT_A_LOGICAL_RAM_WIDTH = 32,
            PORT_B_ADDRESS_CLOCK = "clock1",
            PORT_B_ADDRESS_WIDTH = 11,
            PORT_B_BYTE_ENABLE_CLOCK = "clock1",
            PORT_B_BYTE_ENABLE_MASK_WIDTH = 1,
            PORT_B_BYTE_SIZE = 1,
            PORT_B_DATA_IN_CLOCK = "clock1",
            PORT_B_DATA_WIDTH = 1,
            PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
            PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
            PORT_B_FIRST_ADDRESS = 0,
            PORT_B_FIRST_BIT_NUMBER = 1,
            PORT_B_LAST_ADDRESS = 2047,
            PORT_B_LOGICAL_RAM_DEPTH = 2048,
            PORT_B_LOGICAL_RAM_WIDTH = 32,
            PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
            POWER_UP_UNINITIALIZED = "false",
            RAM_BLOCK_TYPE = "AUTO"
        );
    ram_block2a2 : cycloneii_ram_block
        WITH (
            CON
    .

    .

    .

    And so on, doesn´t seem that there are different things missing...

    Maybe you can give me a tip how I can resolve that problem.

    [EDIT]

    Or please, tell me what informations you need to help out...

    [/EDIT]

    Yours and a preventive thanks,

    Kjellski
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Are the entity names like ram_block2a0 created during synthesis with the errors locating to code in the db directory? If so, look for a problem higher in the hierarchy.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Hello Brad,

    it seems I´ve solved the problem. Not the problem itself, but my problem.

    I´ve just rebuild the design in SOPC-Builder and added my components as I did before. I´ve just not played arround with addings and things like before, just because now the way to go was a bit more clean...

    But after that, the sythesis went through...

    I can look up the module in hirarchy, maybe for the next guy with this problem. Just have to wait until monday...

    Greetings

    Kjellski
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Hey there,

    sorry for the late response, but actually I couldn´t restore the old problem anymore. I don´t know wether this has something to do with it or not, but I was using Quartus at the 7.x edition and I´m still using it. What the main difference between the two times I´ve created that type of structure was:

    I´ve resolved the problems between my pipeline and the Avalond ST interface _before_ I´ve inclueded the pipeline into the SOPC builder _and_ told it to automatically insert timing adapters.

    Hope that this might help someone with the same problem.

    Greetings,

    Kjellski