M4K memory problem in cyclone II 35672c6 device,

Hello Altera Gurus,

I´ve got the same problem as above... my first post here and I´ve already used the search and won´t open a new thread. Isn´t that amazing?

Sorry... to the point:

I´ve used a reference design for CycloneII NiosII Devboard and entered SOPC Builder. Then I wrote my wrapper to connect my pipeline like this:

Avalon MM -> ST -> Pipeline -> Avalon ST -> MM

Then I´ve handled some errors and resolved problems. The system generation was successfull and I´ve updated the block in the .bdf file. Reconnected some wires and started compilation...

After about 900 Warnings the errors occured:

Error: WYSIWYG RAM primitive "ram_block2a0" must have Port A, Address port or parameter specified
Error: WYSIWYG RAM primitive "ram_block2a0" must have Port B, Address port or parameter specified
Error: WYSIWYG RAM primitive "ram_block2a1" must have Port A, Address port or parameter specified

The double click on one of this messages shows the following section:

VARIABLE 
    ram_block2a0 : cycloneii_ram_block
        WITH (
            CONNECTIVITY_CHECKING = "OFF",
            LOGICAL_RAM_NAME = "ALTSYNCRAM",
            MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
            OPERATION_MODE = "bidir_dual_port",
            PORT_A_ADDRESS_WIDTH = 11,
            PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
            PORT_A_BYTE_SIZE = 1,
            PORT_A_DATA_WIDTH = 1,
            PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
            PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
            PORT_A_FIRST_ADDRESS = 0,
            PORT_A_FIRST_BIT_NUMBER = 0,
            PORT_A_LAST_ADDRESS = 2047,
            PORT_A_LOGICAL_RAM_DEPTH = 2048,
            PORT_A_LOGICAL_RAM_WIDTH = 32,
            PORT_B_ADDRESS_CLOCK = "clock1",
            PORT_B_ADDRESS_WIDTH = 11,
            PORT_B_BYTE_ENABLE_CLOCK = "clock1",
            PORT_B_BYTE_ENABLE_MASK_WIDTH = 1,
            PORT_B_BYTE_SIZE = 1,
            PORT_B_DATA_IN_CLOCK = "clock1",
            PORT_B_DATA_WIDTH = 1,
            PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
            PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
            PORT_B_FIRST_ADDRESS = 0,
            PORT_B_FIRST_BIT_NUMBER = 0,
            PORT_B_LAST_ADDRESS = 2047,
            PORT_B_LOGICAL_RAM_DEPTH = 2048,
            PORT_B_LOGICAL_RAM_WIDTH = 32,
            PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
            POWER_UP_UNINITIALIZED = "false",
            RAM_BLOCK_TYPE = "AUTO"
        );
    ram_block2a1 : cycloneii_ram_block
        WITH (
            CONNECTIVITY_CHECKING = "OFF",
            LOGICAL_RAM_NAME = "ALTSYNCRAM",
            MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
            OPERATION_MODE = "bidir_dual_port",
            PORT_A_ADDRESS_WIDTH = 11,
            PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
            PORT_A_BYTE_SIZE = 1,
            PORT_A_DATA_WIDTH = 1,
            PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
            PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
            PORT_A_FIRST_ADDRESS = 0,
            PORT_A_FIRST_BIT_NUMBER = 1,
            PORT_A_LAST_ADDRESS = 2047,
            PORT_A_LOGICAL_RAM_DEPTH = 2048,
            PORT_A_LOGICAL_RAM_WIDTH = 32,
            PORT_B_ADDRESS_CLOCK = "clock1",
            PORT_B_ADDRESS_WIDTH = 11,
            PORT_B_BYTE_ENABLE_CLOCK = "clock1",
            PORT_B_BYTE_ENABLE_MASK_WIDTH = 1,
            PORT_B_BYTE_SIZE = 1,
            PORT_B_DATA_IN_CLOCK = "clock1",
            PORT_B_DATA_WIDTH = 1,
            PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
            PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
            PORT_B_FIRST_ADDRESS = 0,
            PORT_B_FIRST_BIT_NUMBER = 1,
            PORT_B_LAST_ADDRESS = 2047,
            PORT_B_LOGICAL_RAM_DEPTH = 2048,
            PORT_B_LOGICAL_RAM_WIDTH = 32,
            PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
            POWER_UP_UNINITIALIZED = "false",
            RAM_BLOCK_TYPE = "AUTO"
        );
    ram_block2a2 : cycloneii_ram_block
        WITH (
            CON

.

.

.

And so on, doesn´t seem that there are different things missing...

Maybe you can give me a tip how I can resolve that problem.

[EDIT]

Or please, tell me what informations you need to help out...

[/EDIT]

Yours and a preventive thanks,

Kjellski