Altera_Forum
Honored Contributor
15 years agoLVPECL VCCIO 3.3V instead of 2.5V
Hi, I am facing an issue for my PCB which uses Arria2GX FPGA. Due to pin constraints, I am forced to use an LVPECL dedicated clock on a bank which has LVCMOS33 I/Os(Bank 4A for EP2AGX125E device to be exact). I have provided VCCIO as 3.3V but LVPECL (which shares the same VCCIO) requires VCCIO not greater than 2.6V. will this be an issue and cause the clock receiver to fail? I cannot use any other banks because all other clock input pins are used.