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Altera_Forum
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15 years ago

LVPECL VCCIO 3.3V instead of 2.5V

Hi, I am facing an issue for my PCB which uses Arria2GX FPGA. Due to pin constraints, I am forced to use an LVPECL dedicated clock on a bank which has LVCMOS33 I/Os(Bank 4A for EP2AGX125E device to ...
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Altera_Forum
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15 years ago

FvM, thanks for your reply.

Yes, the person who compiles the FPGA build has decided to falsely give LVCMOS25 and generate the build. For LVCMOS this won't be an issue I guess, since noise margins are almost compatible for LVCMOS33 and LVCMOS25. But my worry is whether the 3.3V would cause the LVPECL receiver to malfunction. I am using AC coupling and the differential swing is within the range of Altera spec. Besides, the common mode bias which I have provided is 1.25V(assuming 2.5V)..

since the supply is now 3.3V, should I increase the bias? I still think 1.25V is pretty safe even with 3.3V.