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Altera_Forum
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15 years ago

LVPECL VCCIO 3.3V instead of 2.5V

Hi, I am facing an issue for my PCB which uses Arria2GX FPGA. Due to pin constraints, I am forced to use an LVPECL dedicated clock on a bank which has LVCMOS33 I/Os(Bank 4A for EP2AGX125E device to ...
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Altera_Forum
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15 years ago

Apart from the question, if the differential receiver possibly can work with VCCIO of 3.3V and which performance degradation must be expected, Quartus will require a VCCIO setting of 2.5V for the respective bank to allow an differential I/O standard in it. So you would have to declare all LVCMOS I/Os of bank 4A wrongly as LVCMOS25 in addition.

But you can hardly expect official clearance for unspecified operation of Altera devices, I think.