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Altera_Forum
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15 years ago

LVPECL VCCIO 3.3V instead of 2.5V

Hi, I am facing an issue for my PCB which uses Arria2GX FPGA. Due to pin constraints, I am forced to use an LVPECL dedicated clock on a bank which has LVCMOS33 I/Os(Bank 4A for EP2AGX125E device to ...
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Altera_Forum
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15 years ago

Personally, I expect the receiver to work at 3.3V, the maximum speed most likely reduced. Because Altera won't give a specification for differential receiver operation at 3.3V, you have to acquire the typical data yourself, provide a sufficient margin and hope, that it isn't ruined by device parameter variations.