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MK_ABQ's avatar
MK_ABQ
Icon for Contributor rankContributor
2 years ago
Solved

LVDS

Hi, I am using Intel Arria 10 GX FPGA development kit. DK-DEV-10AX115S-A The development kit has two FMC connectors FMC A and FMC B. There are LVDS standard pins in the connector. I am trying t...
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  • FvM's avatar
    FvM
    2 years ago

    You don't need to connect differential termination to see specified LVDS voltage range. Unterminated pins simply swing to VCCIO and GND for 1 and 0 state. In so far termination isn't required to see LVDS output working. There must be another elementary problem in your test, e.g. probing wrong FMC pins.

AqidAyman_Altera's avatar
AqidAyman_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi,


I seen that you accepted the answer as solution. I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.