Forum Discussion
MK_ABQ
Contributor
ContributorLVDS
Hi, I am using Intel Arria 10 GX FPGA development kit. DK-DEV-10AX115S-A The development kit has two FMC connectors FMC A and FMC B. There are LVDS standard pins in the connector. I am trying t...
You don't need to connect differential termination to see specified LVDS voltage range. Unterminated pins simply swing to VCCIO and GND for 1 and 0 state. In so far termination isn't required to see LVDS output working. There must be another elementary problem in your test, e.g. probing wrong FMC pins.
MK_ABQContributor
ContributorHi,
Yes I double checked quartus pin planner and also fitter report and the pins looks okay and have been assigned correctly, but I am not able to see anything in the LVDS pin.
So, I don't need an LVDS IP ?
