Forum Discussion
ContributorLVDS
You don't need to connect differential termination to see specified LVDS voltage range. Unterminated pins simply swing to VCCIO and GND for 1 and 0 state. In so far termination isn't required to see LVDS output working. There must be another elementary problem in your test, e.g. probing wrong FMC pins.
ContributorHi,
Lets take just one pin for example. Pin 1 refers to an LVDS pin, and yes both P and N of this pin is defined in QSF. My question is, lets say if I drive the LVDS pin as "logic 0" or "logic 1" or say I just toggle 1 and 0 in regular interval, I expect it to show in the acutal hardware when I probe.
I am wondering if just declaring the signal as an output port in VHDL, and assigning the correct pin in qsf is just enough for LVDS?. or I should use any intel IP which has configurations to be able for the signal to propogate in LVDS pin.
Thanks
Super ContributorHi,
check in the Quartus .pin file which pi s have been actually assigned.
The general way is to use a single port pin in top level entity, assign the positive pin of an available pin pair to it in pin planner or assignment editor and specify LVDS IO standard. The negative pin will be assigned automatically, both pins are shown in pin planner.
