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MK_ABQ's avatar
MK_ABQ
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3 years ago
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LVDS

Hi, I am using Intel Arria 10 GX FPGA development kit. DK-DEV-10AX115S-A The development kit has two FMC connectors FMC A and FMC B. There are LVDS standard pins in the connector. I am trying t...
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  • FvM's avatar
    FvM
    3 years ago

    You don't need to connect differential termination to see specified LVDS voltage range. Unterminated pins simply swing to VCCIO and GND for 1 and 0 state. In so far termination isn't required to see LVDS output working. There must be another elementary problem in your test, e.g. probing wrong FMC pins.

MK_ABQ's avatar
MK_ABQ
Icon for Contributor rankContributor
3 years ago

Hi,

Lets take just one pin for example. Pin 1 refers to an LVDS pin, and yes both P and N of this pin is defined in QSF. My question is, lets say if I drive the LVDS pin as "logic 0" or "logic 1" or say I just toggle 1 and 0 in regular interval, I expect it to show in the acutal hardware when I probe.

I am wondering if just declaring the signal as an output port in VHDL, and assigning the correct pin in qsf is just enough for LVDS?. or I should use any intel IP which has configurations to be able for the signal to propogate in LVDS pin.

Thanks