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hariprasathb's avatar
hariprasathb
Icon for New Contributor rankNew Contributor
1 month ago

LVDS TX/RX Pin Assignment Error in Quartus – Unable to Resolve

Hi Team,

 

I am facing a pin assignment issue with LVDS TX and RX IP in Quartus Prime.

I have tried all the suggestions provided earlier (bank selection, I/O standard, refclk, PLL connections, and pin constraints),

but I am still encountering pin assignment errors during compilation.

 

Details:

- Device: AGIB022R31A2I2VB

- Tool: Quartus Prime 25.1.1

- LVDS IP: TX and RX

- Mode: External pll mode in both TX and RX

- Issue: Pin assignment errors related to LVDS TX/RX signals

 

I have verified:

- Correct I/O banks and VCCIO

- Differential pair placement

- Dedicated reference clock usage

- PLL lock status

 

Despite this, the issue persists.

I have attached all relevant files:

- .qsf

 

If possible, could someone please:

1. Review the attached files and point out what might be wrong, OR

2. Share a small working reference project for LVDS TX/RX pin assignment

 

I am also open to discussing this over a call if needed, as it may be easier to debug.

Any guidance would be appreciated.

 

 

 

Thanks & Regards,

Hari

 

Configuration
Generic Io

6 Replies

  • Farabi's avatar
    Farabi
    Icon for Regular Contributor rankRegular Contributor
    1 month ago

    Hello, 

     

    Let me check and get back to you. 

     

    regards,

    Farabi

  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    Icon for Regular Contributor rankRegular Contributor
    1 month ago

    Hi Hari,

     

    Can you share .qar files for me to reproduce the error from my end?

    I did not see it. If possible, you can share it through Private Message.

     

    Regards,

    Aqid

  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    Icon for Regular Contributor rankRegular Contributor
    1 month ago

    Hi Hari,

     

    Can you try to remove all the pin assignments?

     

    If this passes the compilation, then you should follow the pin placement suggested by the fitter, and then it should be good.

     

    It might be the issue with your differential pin and PLL pin placement. Refer guideline below:

    https://docs.altera.com/r/docs/721819/25.3.1/agilextm-7-lvds-serdes-user-guide-f-series-and-i-series/pin-placement-for-differential-channels

     

    Regards,
    Aqid

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    1 month ago

    You may also want to try out Interface Planner.  That will help ensure you can pick legal locations: 

    https://docs.altera.com/r/docs/683143/25.1.1/quartus-prime-pro-edition-user-guide-design-constraints/using-interface-planner