LVDS Signal DC offset and AC Swing

1. It's all in the datasheet.

2. Which pins are you asking about, GPIO or transceiver output? Transceiver don't provide LVDS standard for DC coupled links.

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"High Speed Differential I/O is the dedicated I/O standard for the transmitter in Intel Cyclone 10 GX transceivers"

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I found in earlier documents that LVDS is specified from 1.0V to 1.4V . 0.3V Voltage Swing and Center 1.25V with Clear figures. I assume that same values are same for Cyclone 10 GX and newer devices. I couldn't find the values described like this in Cyclone 10 GX documentation.

For example, at Cyclone 10 GX datasheet ( https://www.altera.com/en_us/pdfs/literature/hb/cyclone-10/c10gx-51002.pdf ) page 19, VCM is defined as 1.25 V and Minimum Voltage swing is defined 200 mV ( 2*VID = 2 * 100 ) . There is no Max value is defined. For the data rates below 700 Mbps Swing from 0 to 1.85V, For data rates above 700 Mbps , Swing from 1,0 V to 1.6V ( For optimized LVDS receiver performance, the receiver voltage input range must be within 1.0 V to 1.6 V for data rates above 700

Mbps and 0 V to 1.85 V for data rates below 700 Mbps. ) is this correct? Am I missing something?

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LVDS outputs in GPIO banks are compatible with industry standard (Vocm 1.25V, 0.3 to 0.4V differential swing).

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is there any limitation in the cyclone 1o gx transceiver to create lvds signal defined as vocm 1.25 v , 0.3v to 0.4v differential swing with 2.5 gbps (1.25 ghz clock) by using the external shared clock with minimum 5 transceivers for source synchronous implementation ( 1 clock 4 data late at 2.5 gbps data rate with 1.25 ghz )?

It's confusing that you are switching between the GPIO (post# 5) and transceiver (post# 7) output specification. As stated, they are different, they have separate paragraphs in the datasheet.

If your link uses a DC balanced coding like 8b/10b, AC coupling can easily shift the transceiver output to LVDS Vocm.

Hi,

1- in order to eliminate confusing, I tried to create a new thread with the new question.

2- The reason to switch Transceiver, because of necessity. LVDS IO Block performance is limited by 1.434 Gbps. I need 2.5 Gbps.

3- I found the following document: It is for Cyclone 5 not for Cyclone 10. I just tried to figure out the capaility of transceiver. I am hoping this is same as Cyclone 10 GX

https://www.altera.co.jp/content/dam/altera-www/global/ja_jp/pdfs/literature/hb/cyclone-v/cv_55002.pdf

Sounds like, the following section of the document says that Vocm is programmable with Transceiver. Am I missing something?

In table 2-2,

A- Please check the second section called "Save Board Space and Cost"

B- From there, please see " On-Chip Biasing "

C- At this section, the comment says " Establishes the required transmitter common-mode voltage (TX VCM) level at the transmitter output. The circuitry is available only if you enable OCT. When you disable OCT, you must implement off-chip biasing circuitry to establish the required TX VCM level. "

Does this mean that Vcm is programmable? Am I missing something?

Why do you refer to Cyclone V GX instead of Cyclone 10 GX documents? The relevant are the transceiver PHY user guide https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-10/ug_cyclone10_xcvr_phy.pdf and the datasheet https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-10/c10gx-51002.pdf

However neither C5GX nor C10GX have programmable transceiver Vocm level. Datasheet specifies 0.65 V for C5GX and 0.4/0.5 V for C10GX. Setting transceiver Vocm to 1.25 V LVDS value is simply impossible due to the low transceiver supply voltage.

You didn't yet answer the question about AC coupling option. What's your application?

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Why do you refer to Cyclone V GX instead of Cyclone 10 GX documents? The relevant are the transceiver PHY user guide https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-10/ug_cyclone10_xcvr_phy.pdf and the datasheet https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-10/c10gx-51002.pdf

However neither C5GX nor C10GX have programmable transceiver Vocm level. Datasheet specifies 0.65 V for C5GX and 0.4/0.5 V for C10GX. Setting transceiver Vocm to 1.25 V LVDS value is simply impossible due to the low transceiver supply voltage.

You didn't yet answer the question about AC coupling option. What's your application?

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A- This is an application of MIPI D-PHY: The physical layer is explained at the following document at page 14 under the slide title called " MIPI D-PHY at the Physical Layer "

https://www.keysight.com/upload/cmc_upload/all/electrical-protocol-and-application-layer-validation-mipi-d-phy-and-m-phy-design.pdf

This is an interface between FPGA(Cyclone 10 GX) and Video Processor ( Intel Movidius ) by using Intel/Altera IP vendor's IP ( Nortwest Logic)

B- In order to meet the physical layer requirements. We are using the following IC from Meticom

http://meticom.com/page2/page17/page19/appexamp01.html

Please see the right section of the figure: Meticom MC20902 IC is used between FPGA source and Video Processor MIPI D-PHY Sink

C- Problem: Cyclone 10 GX devices LVDS lines are limited by 1.434 Gbps

D- Solution: Cyclone 10 GX devices Transceiver lanes will be used to meet the data rate 2.5 Gbps ( DDR rate, it means clock speed will be half = 1.25 Ghz )

E- Transceiver capability for DC offset (Vocm) and AC Swing ( from 0.2V to 0.4V peak to peak) is the key

QUESTION: What is the capability of Cyclone 10 GX transceivers to adjust Vocm and AC Swing?

MY UNDERSTANDING from the discussion above is that we don't have any control on both of Vocm and AC Swing. is this right?