LVDS Signal DC offset and AC Swing

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LVDS outputs in GPIO banks are compatible with industry standard (Vocm 1.25V, 0.3 to 0.4V differential swing).

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is there any limitation in the cyclone 1o gx transceiver to create lvds signal defined as vocm 1.25 v , 0.3v to 0.4v differential swing with 2.5 gbps (1.25 ghz clock) by using the external shared clock with minimum 5 transceivers for source synchronous implementation ( 1 clock 4 data late at 2.5 gbps data rate with 1.25 ghz )?