LVDS Signal DC offset and AC Swing

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Why do you refer to Cyclone V GX instead of Cyclone 10 GX documents? The relevant are the transceiver PHY user guide https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-10/ug_cyclone10_xcvr_phy.pdf and the datasheet https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-10/c10gx-51002.pdf

However neither C5GX nor C10GX have programmable transceiver Vocm level. Datasheet specifies 0.65 V for C5GX and 0.4/0.5 V for C10GX. Setting transceiver Vocm to 1.25 V LVDS value is simply impossible due to the low transceiver supply voltage.

You didn't yet answer the question about AC coupling option. What's your application?

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A- This is an application of MIPI D-PHY: The physical layer is explained at the following document at page 14 under the slide title called " MIPI D-PHY at the Physical Layer "

https://www.keysight.com/upload/cmc_upload/all/electrical-protocol-and-application-layer-validation-mipi-d-phy-and-m-phy-design.pdf

This is an interface between FPGA(Cyclone 10 GX) and Video Processor ( Intel Movidius ) by using Intel/Altera IP vendor's IP ( Nortwest Logic)

B- In order to meet the physical layer requirements. We are using the following IC from Meticom

http://meticom.com/page2/page17/page19/appexamp01.html

Please see the right section of the figure: Meticom MC20902 IC is used between FPGA source and Video Processor MIPI D-PHY Sink

C- Problem: Cyclone 10 GX devices LVDS lines are limited by 1.434 Gbps

D- Solution: Cyclone 10 GX devices Transceiver lanes will be used to meet the data rate 2.5 Gbps ( DDR rate, it means clock speed will be half = 1.25 Ghz )

E- Transceiver capability for DC offset (Vocm) and AC Swing ( from 0.2V to 0.4V peak to peak) is the key

QUESTION: What is the capability of Cyclone 10 GX transceivers to adjust Vocm and AC Swing?

MY UNDERSTANDING from the discussion above is that we don't have any control on both of Vocm and AC Swing. is this right?