New Contributor
Super ContributorHi,
thanks for clarification. I was misleaded by a comment in initial post "for example clock is only running when the transmitter outputs data". This would in fact exclude usage of transmitted clock as PLL reference, or at least require up-to 1 ms lock delay.
Is there any reason why the transmitted clock should be modified depending on data content in the sender? If not, I guess you are seeing just some kind of data-to-clock crosstalk. Or, the worse case, an actually unstable TX PLL clock.
What is the primary problem, do you experience data corruption?
Personally I'd tried to get rid of a dedicated clock channel and use CDR receiver with 8b/10b encoded data.
P.S.: If you are sending unencoded binary data and can't use CDR, TX clock is discontinuous but frequency tightly defined, there is most likely a way to regenerate a continuous clock in a kind of soft PLL.
