New Contributor
New Contributori will clarify,
First we are talking about an existing design which is used for years in multiple systems that are in mass production. I would say that the design is functionally working, we do not see any actual data integrity issues.
The transmitter is an IC which output an 200MHz clock and a few channels of DDR data. The receiver is implemented in a cyclone 10 GX device using the LVDS SERDES IP.
Lately, we found that there are some inconsistency in the IC LVDS output clock behavior and that the clock show some correlation to output data. i.e. the clock does not behave like a free running clock with a constant period and duty cycle. I'm trying to understand if this is an issue and if the LVDS SERDES can handle a clock that is not free running.
see picture below to see clock pulse width variations for data transaction MSB and LSB.
